(1) Field of the Invention
This invention relates to a verification apparatus, verification method, and program and, more particularly, to a verification apparatus, verification method, and program for developing and verifying hardware and software for a system large scale integrated circuit (LSI).
(2) Description of the Related Art
In recent years a long time and high costs have been spent in developing system LSIs due to their scale and multifunctionality. Accordingly, it is hoped that a hardware development and verification environment and software development and verification environment where a desired high-quality system LSI can efficiently be fabricated at a low cost in a short period of time will be built.
FIG. 5 is a schematic diagram of a conventional hardware development and verification environment and a conventional software development and verification environment.
To develop a system LSI, LSI specifications are designed first, then a system is divided into functional modules by designing architecture on the basis of the LSI specifications, and then hardware is separated from software for controlling the hardware.
The hardware includes peripheral circuits for a central processing unit (CPU)/micro processing unit (MPU) included in the system LSI. Usually the operation of the hardware is described in a hardware description language (HDL) on the basis of a description at a behavior level of the logical function of the hardware.
Design data which represents the logical function of the hardware is described at a register transfer level (RTL) on the basis of this operation description. To verify the hardware, a hardware model (RTL model) 101 RTL-described in the HDL in this way is simulated with a test pattern 102 by a logic simulator 103.
In addition, to verify the hardware, the equivalence of the result of the simulation and an expected value obtained from a hardware model (expected value model) 104 at the behavior level, being a basis for the RTL model 101, by the use of the test pattern 102 is verified by an equivalence verification section 105. The function of the RTL model 101 is verified from the viewpoint of whether there is equivalence between the simulation result and the expected value.
Usually a time concept, such as timing with which a process is performed in the hardware, is not considered in this expected value model 104. Processes, such as logic synthesis and layout design, will be performed after the hardware verification.
On the other hand, usually the software is described in a programming language, such as C or C++. A virtual prototype is used for verifying the software. In the virtual prototype,
a peripheral circuit block 106 where the operation of the peripheral circuits for the CPU/MPU is described is connected to a CPU/MPU block 109 where the operation of the CPU/MPU is described via a bus interface 107 and a bus 108 described in, for example, the C language in accordance with the LSI specifications. In addition, software (firmware) 110 to be verified is stored in a memory block 111.
To verify the software by the use of this virtual prototype, a hardware model described in the C language is needed for the peripheral circuit block 106. Usually the RTL model 101 is rewritten in the C language to generate a program (C model) and this program is used as the hardware model at the time of verifying the software. Moreover, an instruction set simulator (ISS) for performing the processing operation of the CPU/MPU is used as a software debugger. As a result, the software will be debugged in an environment which is almost the same as that of the actual circuit.
After the debugging, the verified software is stored in the actual circuit formed on the basis of the hardware verification to verify the entire system.
To reduce time taken to develop a system LSI in this way, recently co-verification in which the RTL model 101 or the expected value model 104 is simulated in synchronization with the operation of the software debugger and in which the results of execution by the software debugger and the logic simulator 103 are compared has also been performed.
Furthermore, to reduce the development period by performing the simulation at a high speed at the time of verifying the hardware, a method for switching between a low-speed fine (high time-precision) simulation performed with an RTL model and a high-speed coarse (low time-precision) simulation performed with a model at the behavior level on the basis of time precision and designated switching time is disclosed (see, for example, Japanese Unexamined Patent Publication No. 10-261002, paragraph nos. [0037]-[0092] and FIG. 1).